(9) Crude Awakening Crude Awakening NAND Gate NAND Gate NOT Gate NOT Gate AND/NOR/OR Gate AND/NOR/OR Gate Always ON Always ON Second Tick Second Tick XOR Gate XOR Gate Bigger OR/AND Gate Bigger OR/AND Gate XNOR Gate XNOR Gate Crude Awakening NAND Gate NOT Gate AND/NOR/OR Gate Always ON Second Tick XOR Gate Bigger OR/AND Gate XNOR Gate Binary Racer Binary Racer Double Trouble Double Trouble Odd Number of Signals Odd Number of Signals Circular Dependency Circular Dependency Counting Signals Counting Signals Half Adder Half Adder Delayed Lines Delayed Lines Double the Number Double the Number Full Adder Full Adder Odd Ticks Odd Ticks Bit Switch Bit Switch Bit Inverter Bit Inverter Byte OR Byte OR Byte NOT Byte NOT Adding Bytes Adding Bytes Negative Numbers Negative Numbers Input Selector Input Selector Signed Negator Signed Negator The Bus The Bus Saving Gracefully Saving Gracefully Saving Bytes Saving Bytes 1 Bit Decoder 1 Bit Decoder 3 Bit Decoder 3 Bit Decoder Logic Engine Logic Engine Little Box Little Box Counter Counter Binary Racer Double Trouble Odd Number of Signals Circular Dependency Counting Signals Half AdderDelayed Lines Double the Number Full Adder Odd Ticks Bit Switch Bit Inverter Byte OR Byte NOT Adding Bytes Negative Numbers Input Selector Signed Negator The Bus Saving Gracefully Saving Bytes 1 Bit Decoder 3 Bit Decoder Logic Engine Little Box Counter Arithmetric Engine Arithmetric Engine Registers Registers Component Factory Component Factory Instruction Decoder Instruction Decoder Calculations Calculations Conditions Conditions Program Program Immediate Values Immediate Values Turing Complete Turing Complete Arithmetric Engine Registers Component Factory Instruction Decoder Calculations Conditions Program Immediate Values Turing Complete Turing Complete RTA Working Computer% 解説 (0.1059 Beta) 4
of Signals Odd Number of Signals Circular Dependency Circular Dependency Counting Signals Counting Signals Half Adder Half Adder Delayed Lines Delayed Lines Double the Number Double the Number Full Adder Full Adder Odd Ticks Odd Ticks Bit Switch Bit Switch Bit Inverter Bit Inverter Byte OR Byte OR Byte NOT Byte NOT Adding Bytes Adding Bytes Negative Numbers Negative Numbers Input Selector Input Selector Signed Negator Signed Negator The Bus The Bus Saving Gracefully Saving Gracefully Saving Bytes Saving Bytes 1 Bit Decoder 1 Bit Decoder 3 Bit Decoder 3 Bit Decoder Logic Engine Logic Engine Little Box Little Box Counter Counter Binary Racer Double Trouble Odd Number of Signals Circular Dependency Counting Signals Half AdderDelayed Lines Double the Number Full Adder Odd Ticks Bit Switch Bit Inverter Byte OR Byte NOT Adding Bytes Negative Numbers Input Selector Signed Negator The Bus Saving Gracefully Saving Bytes 1 Bit Decoder 3 Bit Decoder Logic Engine Little Box Counter Arithmetic / Memory 1. Binary Racer 2. Double Trouble 3. Odd Number of Signals 4. Circular Dependency 5. Counting Signals 6. Half Adder 7. Delayed Lines 8. Double the Number 9. Full Adder 10. Odd Ticks 11. Bit Switch 12. Bit Inverter 13. Byte OR 14. Byte NOT 15. Adding Bytes 16. Negative Numbers 17. Input Selector 18. Signed Negator 19. The Bus 20. Saving Gracefully 21. Saving Bytes 22. 1 Bit Decoder 23. 3 Bit Decoder 24. Logic Engine 25. Little Box 26. Counter Turing Complete RTA Working Computer% 解説 (0.1059 Beta) 15
ON なら LOAD 出力の ENABLE ピンは LOAD の時のみ有効にする 入力2が OFF なら DON'T SAVE 、 ON なら SAVE DON'T SAVE ならメモリを保持 SAVE なら入力の値をメモリに上書き保存 Turing Complete RTA Working Computer% 解説 (0.1059 Beta) 35
に従ってメモリ A0/A1/B0/B1 を切り替える LOAD が有効の時のみ、出力の Enable ピンを 有効にする SAVE が有効の時は VALUE の値を A OR B , 0 OR 1 に従って保存、それ以外は値を保持 Turing Complete RTA Working Computer% 解説 (0.1059 Beta) 38
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![Heavy Spoilers [重度のネタバレ注意] 1. XOR Gate 2. Double Trouble 3.](https://files.speakerdeck.com/presentations/8f6dabe6985f444f96f0546516c172a9/slide_50.jpg){kind=link}
