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NTUST.pdf

terrynini
December 10, 2019
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 NTUST.pdf

terrynini

December 10, 2019
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  1. JazelleⓇ TrustZoneⓇ ARM ARMv5 ARMv6 ARMv7-A/R ARMv8-A SIMD NEONTM Adv

    SIMD VFPv2 VFPv3/v4 ThumbⓇ-v2 A32+T32 ISAs AArch32 A64 ISA AArch64 CRYPTO CRYPTO
  2. ARM $ arm-linux-gnueabi-gcc -march=armv7-a -mthumb hello.c -o hello 000103fc <main>:

    103fc: b580 push {r7, lr} 103fe: af00 add r7, sp, #0 10400: f240 4084 movw r0, #1156 ; 0x484 10404: f2c0 0001 movt r0, #1 10408: f7ff ef68 blx 102dc <puts@plt> 1040c: 2300 movs r3, #0 1040e: 4618 mov r0, r3 10410: bd80 pop {r7, pc} Thumb
  3. ARM 000103fc <main>: 103fc: e92d4800 push {fp, lr} 10400: e28db004

    add fp, sp, #4 10404: e59f0014 ldr r0, [pc, #20] ; 10420 <main+0x24> 10408: ebffffb3 bl 102dc <puts@plt> 1040c: e3a03000 mov r3, #0 10410: e1a00003 mov r0, r3 10414: e24bd004 sub sp, fp, #4 10418: e8bd4800 pop {fp, lr} 1041c: e12fff1e bx lr 10420: 00010494 .word 0x00010494 $ arm-linux-gnueabi-gcc -march=armv7-a hello.c -o hello ARM
  4. ARM r0~r10 general purpose r11 FP Frame Pointer r12 IP

    Intra Procedural Call r13 SP Stack Pointer r14 LR Link Register r15 PC Program Counter CPSR Current Program Status Register register
  5. ARM MOV R1, #0xFA05 MOV R0, #256 MOVW R3, #0xBEEF

    MOVT R3, #0xDEAD MVN R2, #0xF R0 R1 R2 R3 R4 0x00000100 0x0000FA05 0xFFFFFFF0 0xDEADBEEF mov
  6. ARM MOV R1, #0xFA05 MOV R0, #256 MOVW R3, #0xBEEF

    MOVT R3, #0xDEAD MVN R2, #0xF MOV R4, R0, LSL #1 R0 R1 R2 R3 R4 0x00000100 0x0000FA05 0xFFFFFFF0 0xDEADBEEF 0x00000200 mov 有時候 mov 會噴錯是因為編碼問題,關鍵字 Modified immediate constants in ARM instructions
  7. ARM AND R0, R1, R2 ;r0 = r1&r2 ORR R0,

    R1, R2 ;r0 = r1|r2 EOR R0, R1, R2 ;r0 = r1⊕r2 logical
  8. ARM mov r0, #0x1000 mov r1, #0x100 str r1, [r0]

    ldr/str 0x100 0x1000 0x1004 0x1008 0x100C 0x1010 0x1014
  9. ARM mov r0, #0x1000 mov r1, #0x100 str r1, [r0]

    ldr r2, [r0] add r2, r2, #1 str r2, [r0, #4] ldr/str 0x100 0x101 0x1000 0x1004 0x1008 0x100C 0x1010 0x1014
  10. ARM mov r0, #0x1000 mov r1, #0x100 str r1, [r0,

    #4] ldr/str 0x100 0x1000 0x1004 0x1008 0x100C 0x1010 0x1014 r0 0x1000
  11. ARM mov r0, #0x1000 mov r1, #0x100 str r1, [r0,

    #4]! ldr/str 0x100 0x1000 0x1004 0x1008 0x100C 0x1010 0x1014 r0 0x1004
  12. ARM mov r0, #0x1000 mov r1, #0x100 str r1, [r0],

    #4 ldr/str 0x100 0x1000 0x1004 0x1008 0x100C 0x1010 0x1014 r0 0x1004
  13. ARM str r1, [r0, #4] str r1, [r0, r2] str

    r1, [r0, r2, LSL#2] ldr/str
  14. ARM N negative 1: result is negative Z zero 1:

    result is zero C carry set to 1 if add produced a carry set to 0 if sub produced a borrow V overflow set to 1 if the result of an add, subtract, or compare is greater than or equal to 231, or less than -231 T Thumb 0: arm mode, 1: thumb mode E Endian 0: little endian, 1: bit endeian CPSR ARM and Thumb-2 Instruction Set Quick Reference Card
  15. ARM conditional execution .global main main: mov r0, #2 cmp

    r0, #3 addlt r0, r0, #1 cmp r0, #3 addlt r0, r0, #1 bx lr
  16. ARM conditional execution r0 = 2 if( r0 < 3)

    r0 += 1 if( r0 < 3) r0 += 1 return r0
  17. ARM conditional execution CMP R1, #3 
 ITT EQ 


    LDREQ R1, [R5] LDREQ R2, [R5] if( r1 == 3 ){ r1 = *r5 r2 = *r5 }
  18. ARM conditional execution CMP R1, #3 
 ITTE EQ 


    LDREQ R1, [R5] LDREQ R2, [R5] ADDNE R1, #1 if(r1 == 3){ r1 = *r5 r2 = *r5 }else{ r1 += 1 }
  19. ARM branch .global main main: mov r0, #1 mov r1,

    #2 loop: cmp r0, #1024 beq end mul r0, r0, r1 b loop end: bx lr
  20. ARM .text .global _start _start: .code 32 add r2, pc,

    #1 bx r2 .code 16 mov r0, #1 branch