++ new IfuConnectConfig ) class Default2Config extends Config( new BaseConfig ++ new Bus64BitConfig ++ new IfuNotConnectConfig ) class Bus64BitConfig extends Config((site, here, up) => { case BusWidthBytes => 64 / 8 case AddrSize => 0x200 * here(BusWidthBytes) }) class IfuConnectConfig extends Config((site, here, up) => { case ConnectIfu => true }) case object BusWidthBytes extends Field[Int] case object ConnectIfu extends Field[Boolean] case object AddrSize extends Field[Int] class core_complex(txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val memory = LazyModule(new TLRAM(AddressSet(0x0, p(AddrSize)-1), beatBytes = p(BusWidthBytes))) object Generator { final def main(args: Array[String]) { val p = (new Default2Config).toInstance Driver.emitVerilog( new TestHarness()(p) )