Raven-1 7th RISC-V Workshop 6th RISC-V Workshop RISC-V Processor Raven-2 RISC-V Processor Raven-3 5th RISC-V Workshop 4th RISC-V Workshop 3th RISC-V Workshop 1th RISC-V Workshop 2th RISC-V Workshop User-Level ISA Ver. 1.0 User-Level ISA Ver. 2.0 User-Level ISA Ver. 2.1 User-Level ISA Ver. 2.2 Privileged ISA Ver. 1.7 Privileged ISA Ver. 1.9 Privileged ISA Ver. 1.10 世界発の商用 RISC-Vボード 研究チップの制御 プロセッサとして利用 ヘネパタ第6版は RISC-Vで刷新 パタヘネのRISC-V 版が登場 約半年に1回の頻度で Workshop開催 8th RISC-V Workshop in Barcelona RISC-V Day in Shanghai 9th RISC-V Workshop in Chennai RISC-V Day in Tokyo RISC-V Day in MICRO51 RISC-V Summit in Santa Clara Linuxが動作す るRISC-Vボード 2018 ◼ 2015年から定期的にWorkshopを開催 ◼ トップカンファレンスにRISC-Vネタで 通している。 ◼ パタヘネ・ヘネパタはRISC-Vに移行 ◼ 2017年/2018年に日本でイベント開催
Exynos 9820 began in January this year, and the Samsung engineer appears to have been working on a 5G RF chip based on the RISC-V architecture ever since May 2017, which could reinforce a 2019 release for the 5G smartphones. (https://www.notebookcheck.net/Samsung-Exynos-9820-SoC-and-5G-RF-chips-already-in-the- works.295886.0.html) WD、同社製品搭載のプロセッサ/コントローラなどをRISC-Vへ移行 (https://pc.watch.impress.co.jp/docs/news/1094891.html) NVIDIA gave a presentation about how its proprietary Falcon (Fast Logic CONtroller) core will be replaced by RISC-V cores. (https://www.electronicdesign.com/industrial-automation/rise-risc-v-display-workshop) Internal Project to demonstrate ability to easily develop custom RISC-V implementation by leveraging Rocket Chip. (https://content.riscv.org/wp-content/uploads/2018/05/13.15-13.30-matt-Cockrell.pdf) BSC is promoting the adoption of RISC-V as a key partner of the European Processor Initiative, the consortium to design and develop Europe’s low-power processors and related technologies for extreme- scale, high-performance computing, which will be funded by the European Commission under the Horizon 2020 program. (https://insidehpc.com/2018/05/bsc-host-risc-v-workshop-road- european-processor-initiative/)
RV64Cという 圧縮命令を活用する。 → フェッチサイズを圧縮できる。 Computer Architecture Research with RISC-V Krste Asanovic より抜粋 ISA Shootout: Comparing RISC-V, ARM, and x86 on SPECInt 2006 より抜粋 RV32GC / RV64GCでは、多くの ベンチマークプログラムで他の 命令セットよりも優れる。
GitHubで公開されている (https://github.com/firesim) 大規模FPGAの購入にはかなりのコスト高。200~300万円 FPGAを常に手元に置いておく必要がない。 必要な時に必要な分だけコストがかかる。 → コストダウン・参入障壁を下げる一要因になることを期待 FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud http://iscaconf.org/isca2018/slides/1A3.pdf